M-986-2A1PL【PDF 7/13 页】IC TRANSCEIVER MF 2CHAN 44-PLCC

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Sheet目录2007

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M-986-2A1

www.clare.com

Rev. 3

Initial Configuration: The configuration of the M-986-

2A1 immediately after a reset will be as follows:

channel disabled

2-of-6 input/output

external serial and serial frame clocks.

Also, the M-986-2A1 will place a 00 hex on the

coprocessor port to indicate to the host processor that

it is working.

Transmit Tone Command

The transmit tone command allows the host processor

to transmit any two of the 6 R1 MF frequencies. The

format of the command depends on whether the M-

986 is configured for binary format or 2-of-6 format.

Recieved Tone Detection

When a tone is detected by the M-986, the TBLF out-

put goes low, indicating reception of the tone to the

host processor. The host processor can determine

which tone was detected and which channel the tone

was detected on by reading data from the M-986

coprocessor port. The M-986 will return a single byte

indicating the tone received and the channel that the

tone was received on. The format of the returned byte

depends on whether the M-986 is configured for bina-

ry or 2-of-6 coding.

Coprocessor Port

Commands are written to the M-986 via the coproces-

sor port, and data indicating the received R1 MF tone

is read from the coprocessor port.

Writing to the Coprocessor Port: The following

sequence describes writing a command to the M-986.

(1) The WR signal is driven low by the host processor.

(2) The RBLE (receive buffer latch empty) signal tran-

sitions to a logic high level.

(3) Data is written from D7-D0 to the receive buffer

latch (D7-D0) when the WR signal goes high.

(4) The RBLE signal transitions to a logic low level

after the M-986 reads the data. This signals the host

processor that the receive buffer is empty.

Note: The RBLE should be low before writing to the

coprocessor.

Reading the Coprocessor Port: The following

sequence describes reading received tone informa-

tion from the coprocessor port.

(1) The TBLF (transmit buffer latch full) port pin on the

M-986 goes low indicating the reception of a tone.

(2) The host processor detects the low logic level on

the TBLF pin either by polling a connected port pin or

by an interrupt.

(3) The host processor drives the RD signal low.

(4) The TBLF (transmit buffer latch full) signal transi-

tion to a logic high level.

Configuration

Configuration Byte 1

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ECLK

IOM

ENCI

KPL1

KPEN1

ECLK

Channels 1 & 2

1 = External codec clock; 0 = Internal codec clock

IOM

Channels 1 & 2

1 = Binary input/output; 0 = 2-of-6 input/output

ENC1

Channel 1

1 = Enable channel; 0 = Disable channel

KPL1

Channel 1

1 = 55 ms detection time for KP; 0 = 30 ms detection time for KP

KPEN1

Channel 1

1 = Enable MF tone detection after KP detection;

0 = MF tone detection always on

Configuration Byte 2

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

AMU

ENC2

KPL2

KPEN2

AMU

Channels 1 & 2

1 = A-law Encoding, 0 = m-law Encoding

ENC2

Channel 2

1 = Enable channel; 0 = Disable channel

KPL2

Channel 2

1 = 55 ms detection time for KP; 0 = 30 ms detection time for KP

KPEN2

Channel 2

1 = Enable MF tone detection after KP detection;

0 = MF tone detection always

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